FPGA Engineering Manager

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  • Northwoodspace
  • Torrance, CA
  • Full-Time
  • 4 days ago
  • $208K – $304K
Northwoodspace
Published
May 5, 2026
Location
Torrance, Canada
Job Type

FPGA Engineering Manager: our view in 3 lines...

  • The Role: Lead and manage FPGA design and team for phased array systems integrating high-speed signal processing and data transport in a space infrastructure company.
  • The Person: Own FPGA design for phased array systems, guide architecture and interfaces, mentor and grow a team of FPGA engineers, and develop FPGA processes and automated infrastructure.
  • Requirements: Expert in RTL Design (SystemVerilog or VHDL), experience with FPGA SoCs like Zynq, FPGA build systems and automated testing, DSP or networking on FPGA, schematic review and hardware bring-up, and proficient in Python.

Job Description

About Northwood:

Northwood is a modern space infrastructure company focused on connecting space and Earth. The world runs on space. Space will run on Northwood. Our global ground network ensures that missions ranging from national security, to global connectivity, to disaster response can unlock their full potential and operate every day without fail.

Role:
As Head of FPGA at Northwood Space, you will be responsible for executing on our ambitious digital roadmap to connect Earth and space. You would own the FPGA design for Northwood’s phased array systems, which integrate high-speed signal processing and data transport. Simultaneously, you would be laying a strong foundation with FPGA best practices and automated infrastructure. As a player-coach, you lead by example and by providing the context and mentorship for team success.

Responsibilities:

  • Lead: Guide project architecture and work with other teams to nail down interfaces and requirements. Plan and prioritize work for the FPGA team to deliver mission-critical projects on aggressive timelines.

  • Grow the team: Mentor and develop the existing team of ~5 FPGA engineers, in addition to recruiting new talent to support upcoming projects.

  • Build strong foundations: Steer the development of FPGA internal processes and infrastructure that allows the team to move rapidly.

  • Stay Sharp: Dive in as deep as necessary to keep projects moving.

Basic Qualifications:

  • 7-10+ years of professional experience and typically at least a Bachelors in Electrical Engineering, Computer Engineering, etc.

  • Demonstrated ability to manage teams and lead complex projects

  • Expert in RTL Design (SystemVerilog or VHDL)

  • Experience working on FPGA SoCs like Zynq or similar

  • Experience with FPGA build systems and automated testing

  • Experience with DSP and/or networking on FPGA

  • Experience with schematic review and hardware bring-up

  • Proficient in Python

  • Strong work ethic and drive to succeed

  • Ability to thrive in a fast paced and demanding start-up atmosphere

  • Willing to work extended hours and weekends as needed

  • In-person in Torrance

Nice to have:

  • Startup experience

  • Aerospace experience

  • Experience with C/C++ or rust

Additional Information:

To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.

Northwood is an Equal Opportunity Employer; employment with Northwood is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Key Skills
? Key Skills in dark blue have been inferred based on similar industry roles
VHDL Zynq (FPGA Soc) FPGA Build Systems Automated Test Frameworks Digital Signal Processing (DSP) Hardware Bring-up Python Rust C Systemverilog

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