HOME None Senior Mask Layout Design Engineer
  • NVIDIA
  • Taiwan,
  • Full-Time
  • 81 days ago
NVIDIA VERIFIED EMPLOYER

Senior Mask Layout Design Engineer.

None Full-Time

Senior Mask Layout Design Engineer: our view in 3 lines...

  • The Role:A senior engineer responsible for performing physical mask layout for high-speed mixed-signal and I/O circuits in advanced CMOS technologies for VLSI products.
  • The Person:Perform physical layout and floor planning for mixed-signal functions including PLLs, SerDes and high-speed memory I/Os and verify layouts against design rules and schematics for integration into VLSI products.
  • Requirements:Expertise with Cadence custom circuit design tools particularly Virtuoso, experience running and debugging DRC and LVS with tools such as Dracula, Hercules, Calibre, BSEE with minimum five years mask design/layout experience, and proficiency in perl and python.

About the role

We are looking for a Senior Mask Layout Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling challenge high-speed mixed-signal circuit designs.

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence.

What you'll be doing:

  • Perform physical layout for mixed-signal functions like PLL's, high speed memory I/O circuits, SerDes, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS FinFET technologies using Cadence tools
  • Work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products
  • Job duties will include floor planning, custom layout and verifying against design rules and schematics

What we need to see:

  • BSEE with a minimum of 5 years of relevant mask design / layout experience or equivalent experience
  • Proven understanding of analog circuit layout concepts in submicron CMOS technologies
  • Expert with Cadence custom circuit design tools - particularly virtuoso
  • Experience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre,
  • Able to communicate in spoken and written English
  • Work effectively in a team, good interpersonal skills, enthusiasm and positive energy.
  • Proficiency in scripting languages like perl, python, skill etc.
  • Knowledge of DRC and LVS checking flows, ability to customize DRC and LVS decks

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

Published June 25, 2026
Location Taiwan, Taiwan
Category None  
Job Type Full-Time