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4 4123 LSI India Research & Development Private Limited VERIFIED EMPLOYER

DFT Engineer.

Hardware & Semiconductor Engineering Full-Time

DFT Engineer: our view in 3 lines...

  • The Role:This role is for an experienced DFT engineer working on silicon bring-up, yield analysis, and test pattern development.
  • The Person:The person will work on MBIST and scan insertion, ATPG, ATE pattern development, yield analysis, silicon debugging, and DFT implementation with design, verification, implementation, ATE, and product development teams.
  • Requirements:The ideal candidate has 8+ years of related experience, a strong understanding of DFT techniques, experience in silicon bring-up and yield improvement, and proficiency with Perl or other scripting languages.

About the role

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Job Description:

As a member of our team, you will be responsible for various aspects of DFT, including MBIST and scan insertion, ATPG, ATE pattern development, and yield analysis.
Key Responsibilities:
  • Work closely with the ATE engineer on yield improvement and analysis.
  • Develop ATE patterns, manage the hand-off process, and perform silicon debugging.
  • Participate in block and chip-level DFT implementation, developing and executing all related tasks.
  • Work on DFT lint checking, MBIST architecture, logic insertion, and scan insertion using industry-standard tools.
  • Perform ATPG and pattern simulation for both MBIST and scan.
  • Collaborate with the design, verification, and implementation teams during the DFT design phase, and with the ATE and product development teams during silicon bring-up.
  • Engage with various cross-functional team members, with opportunities to enhance our DFT design methodology.
Required Qualifications:
  • Bachelors in Engineering and 8+ years of related experience or Masters degree and 6+ years of related experience
  • Required experience in silicon bring-up and yield improvement.
  • Solid understanding of DFT techniques.
  • Proven experience in RTL lint checking, scan compression, scan insertion, and the ATPG process.
  • Experience in MBIST architecture and insertion.
  • Experience in analyzing and debugging simulation failures.
  • Solid understanding of digital logic fundamentals.
  • Strong knowledge of the Mentor Tessent/Synopsys DFT and simulation tool suite.
  • Proficiency with Perl or other scripting languages.
  • Strong communication and interpersonal skills.
  • Plus: Experience in STA constraint development in DFT modes

Compensation and Benefits

The annual base salary range for this position is USD 109,700.00 To USD 175,500.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Published August 26, 2026
Location Austin, TX
Job Type Full-Time