HOME Hardware & Semiconductor Engineering Staff Design Engineer, Networking, Google Cloud
  • Google
  • Tel Aviv-Yafo, Tel-Aviv District
  • 9 days ago
Google VERIFIED EMPLOYER

Staff Design Engineer, Networking, Google Cloud.

Hardware & Semiconductor Engineering

Staff Design Engineer, Networking, Google Cloud: our view in 3 lines...

  • The Role:This role is for a hardware engineer who designs networking chips that accelerate data center operations.
  • The Person:The person will lead an ASIC subsystem, define hardware/software interfaces and micro architecture specifications, and collaborate with software, verification, and physical design teams to ensure designs are complete, correct, and performant.
  • Requirements:The ideal candidate has 10 years of experience architecting networking ASICs from specification to production, plus experience developing RTL for ASIC subsystems and cross-functional work in micro-architecture, verification, logic synthesis, and timing closure.

About the role

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 10 years of experience architecting networking ASICs from specification to production.
  • Experience developing Register-Transfer Level (RTL) for ASIC subsystems.
  • Experience with cross-functional engagement in micro-architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications:

  • Experience working with software teams optimizing the hardware/software interface.
  • Experience architecting networking switches, end points, and hardware offloads.
  • Experience working with design networking like: remote direct memory access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.
  • Experience in transmission control protocol (TCP), IP, ethernet, peripheral component interconnect express (PCIE) and dynamic random access memory (DRAM) including network on chip (NoC) principles and protocols (e.g., AXI, ACE, and CHI).
  • Proficiency in procedural programming language (e.g., C++, Python, Go).
  • Understanding of packet classification, processing, queuing, scheduling, switching, traffic conditioning, and telemetry.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be part of a team developing application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.You will also be responsible for performance analysis for a networking stack using your knowledge.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

  • Lead an ASIC subsystem.
  • Understand how it interacts with software and other ASIC subsystems to implement data center networks.
  • Define hardware/software interfaces. Write micro architecture and design specifications.
  • Define efficient micro-architecture and block partitioning/interfaces and flows.
  • Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

In most instances, this position requires in-person interviews as part of the hiring process.

Published October 26, 2026
Location Tel Aviv-Yafo, Israel