- Silabs India Private Limited
- Austin, TX
- Full-Time
- 5 days ago
Design Engineer II.
Before you go
Before you leave us, sign up for our email alerts
We don't do job spam, just the best digital jobs delivered straight to your inbox.
Design Engineer II: our view in 3 lines...
- The Role:This role is for a digital design engineer who develops low-power System on a Chip devices for the wireless IoT market.
- The Person:The person will develop SoC architectures, write System Verilog RTL, perform logic synthesis and timing and power analysis, and support validation of designs on silicon.
- Requirements:The ideal candidate has a Master's degree in Electrical Engineering, 3 to 5 years of professional experience in digital CMOS IC design, Verilog RTL design, and knowledge of embedded processor systems and C coding.
About the role
Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.
Digital Design Engineer II  Â
Austin, TXÂ
The RoleÂ
As a Digital Design Engineer II you will develop world class, highly integrated, low power, System on a Chip devices to serve the IoT wireless market. Â
Â
ResponsibilitiesÂ
- Develop complex SoC/chip Architectures with multiple processors, digital and mixed signal subsystems, multiple power, and clock domains with a goal towards optimizing power for specific customer scenarios.Â
- RTL design of modules through System Verilog HDL coding, adhering to quality standards.Â
- Prepare and hold architecture, design, and verification reviews with technical staff throughout project lifecycleÂ
- SoC level configuration and integration of digital and mixed-signal IPs.  Examples include embedded processors, memory and controllers, busses, power and clocking systems, security systems, machine learning, radio systems, analog IP, and pads.Â
- Perform logic synthesis, full chip timing and power analysis to optimize designs for key customer scenarios.Â
- Experience in working with backend team to optimize design for power performance and area.Â
- Pre-silicon verification utilizing a combination of block/chip-level test benches.Â
- Validation/bring-up of designs on silicon, providing support to cross-functional teamsÂ
Skills You Will Need  Â
Minimum Qualifications: Â Â
- Master’s degree in Electrical EngineeringÂ
- 3-5 years of professional experience in digital CMOS IC designÂ
- Verilog RTL design with demonstrated experience of taking designs through the silicon development lifecycle to productionÂ
- Knowledge of embedded processor systems and C codingÂ
- Experience with logic simulators for both RTL and gate-level simulation, design/waveform browsers, and power analysis toolsÂ
- Experience with logic synthesis and timing constraintsÂ
- Experience in working with analog and mixed signal designs, to support design integration and verification of these subsystems in SOC.Â
- Experience with scripting and automation.  Knowledge of Python, Perl, and TclÂ
- Experience with revision control and configuration management systems (such as Perforce, Git, Methodics)Â
- Excellent written and verbal communications skillsÂ
- Demonstrated ability to generate high output in a self-driven mannerÂ
- Experience with artificial intelligence (AI) powered tools and technologies used to enhance productivity, analysis, and decision-making
Benefits & Perks Â
You can look forward to the following benefits:Â
  Â
- Great medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental and vision plansÂ
- Highly competitive salaryÂ
- 401k plan with match and Roth plan optionÂ
- Equity rewards (RSUs)Â
- Life/AD&D and disability coverageÂ
- Flexible spending accountsÂ
- Adoption assistanceÂ
- Back-Up childcareÂ
- Additional benefit options (Commuter benefits, Legal benefits, Pet insurance)Â
- Flexible PTO scheduleÂ
- 3 paid volunteer days per yearÂ
- Charitable contribution matchÂ
- Tuition reimbursementÂ
- Free downtown parkingÂ
- Onsite gymÂ
- Monthly wellness offeringsÂ
- Free snacksÂ
- Company updates with our CEOÂ
Â
#LI-KB1Â
#LI-HybridÂ
Â
The annualized base pay range for this role is expected to be between $101,500 - $188,500 USD. Actual base pay could vary based on factors including but not limited to experience, geographic location where work will be performed and applicant’s skill set. The base pay is just one component of the total compensation package for employees. Other rewards may include an annual cash bonus, equity package and a comprehensive benefits package.
Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.

