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HOME Hardware & Semiconductor Engineering ASIC Design Verification Engineer, Google TPU
  • Google
  • Sunnyvale, CA
  • 6 days ago
  • $138,000–$197,000 / year
Google VERIFIED EMPLOYER

ASIC Design Verification Engineer, Google TPU.

Hardware & Semiconductor Engineering
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ASIC Design Verification Engineer, Google TPU: our view in 3 lines...

  • The Role:This role is for a hardware engineer who verifies complex digital chip designs used in AI and machine learning acceleration hardware.
  • The Person:The person will plan verification of complex digital design blocks, write coverage measures, debug tests with design engineers, close coverage to find verification holes, and create a constrained-random verification environment using SystemVerilog and UVM.
  • Requirements:The ideal candidate has a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience, 4 years of experience with design verification, and experience with SystemVerilog/Verilog.

About the role

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 4 years of experience with design verification.
  • Experience with SystemVerilog/Verilog.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • 6 years of experience with silicon design verification.
  • Experience with industry-standard simulators, revision control systems and regression systems.
  • Experience contributing across the entire design and verification life cycle.
  • Knowledge of ASIC standard interfaces.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As an ASIC Design Verification Engineer, you will use design and verification expertise to perform direct verification in active projects using problem-solving skills.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

  • Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
  • Identify and write all types of coverage measures for stimulus and corner cases.
  • Debug tests with design engineers to deliver functionally correct design blocks.
  • Close coverage measures to identify verification holes and to show progress towards tape-out.
  • Create a constrained-random verification environment using SystemVerilog and UVM.
Application Instructions: In most instances, this position requires in-person interviews as part of the hiring process.
Published November 5, 2026
Location Sunnyvale, CA
Category Hardware & Semiconductor Engineering  

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