FE Engineering.

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Description

APPLE INC has the following available in Austin, Texas. Write System Verilog RTL code based on microarchitecture specs for GPU components; Simulate and debug RTL using CAD tools to ensure design correctness. Synthesize the design and analyzing area, power, and timing reports to verify PPA goals. Work with verification engineers to review test plans, debug failures, and ensure full coverage. Collaborate with backend and synthesis teams to review placement and routing feedback and make design adjustments accordingly. Participate in design and architecture reviews to discuss interface definitions, data flows, and module responsibilities. Perform timing analysis and optimize design logic to meet critical path constraints. Coordinate with cross-functional team members to align schedules, resolve issues, and support the integration of my module into the full chip. 40 hours/week.

Minimum Qualifications

Master’s degree or foreign equivalent in Electrical and Computer Engineering or related field.

Experience and/or education must include:

Experience in Computer Architecture and Microarchitecture for contributing to the microarchitecture of different GPU blocks
Experience with RTL Coding Using System Verilog
Experience with performing synthesis and timing Analysis for area and power optimizations.
Utilizing CAD Tools for debug and synthesis.
Experience with VLSI Design to design GPUs
Experience with scripting languages such as Perl/Python
Experience with working on GPUs

Preferred Qualifications

N/A