- Apple
- Israel, South District
- Full-Time
- <48 Hours
IP Pixel RTL Design Engineer.
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IP Pixel RTL Design Engineer: our view in 3 lines...
- The Role:This role is for an experienced logic design engineer working on image signal processing intellectual property for pixel processing hardware.
- The Person:The person will help architect next-generation ISP designs, implement RTL micro-architecture, help define specifications, test and verify designs, and work with CAD and PD teams to implement RTL into GDS.
- Requirements:The ideal candidate has 6+ years of Logic Design experience, advanced knowledge of ASIC RTL design methodologies, excellent knowledge of System Verilog and Verilog, and good knowledge of C / C++.
About the role
Taking a picture with an iPhone is an amazing experience. Taking a part in developing the next generation is even more.
The HDC pixel group is working on Apple ISP (Image Signal Processing) IP development. The group implements highly complex cutting-edge image processing technologies, putting emphasis on quality and security, while meeting aggressive area and power constraints.
Description
In this role you'll participate in the architecture of next generations of Apple ISP, handle RTL implementation of the micro-architecture, participate in clearly defining specification, testing and verification of the designs. You will work in collaboration with CAD & PD teams to implement RTL design into GDS, run various flows and provide guidelines to other designers and participate in establishing CAD and design methodologies for correct by construction designs.
At Apple, we’re not all the same. And that’s our greatest strength. We draw on the differences in who we are, what we’ve experienced, and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. We will work with applicants to make any reasonable accommodations.
Minimum Qualifications
6+ years of Logic Design experience
Advanced knowledge of ASIC RTL design methodologies
Advanced knowledge of standard ASIC verification flows including simulation and testbench development
Working knowledge of frontend tools (Synthesis, STA, etc’)
Excellent knowledge of System Verilog, Verilog
Good knowledge of C / C++
Experience with either Python/Perl/Tcl scripts
Knowledge of industry standard interfaces and experience with multiple frontend simulators/debuggers
A teammate with excellent interpersonal skills and the desire to pursue diverse challenges
Preferred Qualifications
BS.c / MS.c EE or BS.c / MS.c CE
Hands-on experience with signal processing design
Knowledge of formal verification & methodologies