- Apple
- Munich, BY
- Full-Time
- 8 days ago
STA Engineer (M, F, D).
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STA Engineer (M, F, D): our view in 3 lines...
- The Role:This position focuses on static timing analysis for semiconductor chip designs, with responsibility for timing signoff across blocks and full chips.
- The Person:The person will develop automated block and full chip signoff flows, drive full chip timing and noise convergence, enable hierarchical timing flows, and work with design, DFT, architecture and power teams to close work.
- Requirements:The ideal candidate holds an MSEE or equivalent strong experience in Static Timing analysis, has extensive experience with one of the commercial STA tools, and can fluently speak and write in English.
About the role
We are looking for talented engineers to join our STA team. In this role, you will be working closely with multiple integration teams, like DFT, Top Level PNR, PHY designers and PNR teams.
Description
You will be responsible for:
Developing automated block and full chip level signoff flows
Full Chip Timing/Noise convergence and full signoff for high quality TO
Enabling hierarchical Timing flows
Power optimizations
Generating block level budget and context for correlation with Full Chip
Driving custom IP integration and custom timing checks flows
Closing work with Design, DFT, architecture and Power team
Minimum Qualifications
Minimum Qualifications
You hold a MSEE or equivalent strong experience in Static Timing analysis
Extensive experience with one of the commercial STA tools
Ability to fluently speak and write in English.
Preferred Qualifications
Familiarity with hierarchical design approach, top-down design, timing and physical convergence
Experience with backend STA closure and Signoff
Deep understanding of designs' constraints development
Good understanding of AC timing from specs to implementation
Good understanding of DFT modes and their constraints
Good communication skills and team player
Quick learning of flows and methods
Advantage - Understanding noise and signal integrity effects
Advantage - Timing margins fundamental from synthesis to signoff
Advantage - Experience with scripting