- Apple
- Austin, TX
- Full-Time
- 5 days ago
Validation CAD Engineer.
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Validation CAD Engineer: our view in 3 lines...
- The Role:This role is for a CAD engineer working on formal verification flows for next-generation processor and SoC development.
- The Person:The person will develop, maintain and enhance formal verification flows, support detailed application profiling and tuning, and work on continuous integration and deployment pipelines and large scale compute cluster management.
- Requirements:The candidate needs experience scripting in Python, Perl, Kotlin or TCL, software development with test in mind, Verilog and System Verilog, and a BS with 3+ years of relevant industry experience.
About the role
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions.
Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices! In the CAD organization, you will get to create new software and technologies that will enable other Apple engineers create products for millions of customers across the world.
Description
Formal Verification CAD engineering plays a major role in promoting a reliable work environment for Formal Verification teams. There are many applications within the formal verification arena that need support and development, such as formal property checking, low power, connectivity checks, sequential equivalence checking (SEC), and coverage. As member of our CAD team, you will develop, maintain, and enhance the flows that our internal teams use to create the next generation of Apple products. In addition to maintaining and enhancing our Formal Verification flow, the position offers a large variety of opportunities ranging from detailed application profiling and tuning to development of Continuous Integration/Deployment pipelines to large scale compute cluster management. You will have the opportunity to integrate your ideas and add new features to the system as well as collaborate with other CAD teams in various functional front-end areas.
Minimum Qualifications
Experience scripting in Python, Perl, Kotlin or TCL
Experience in Software Development with Test in-mind
Knowledge in Verilog and System Verilog
Minimum requirement of BS and 3+ years of relevant industry experience
Preferred Qualifications
Familiarity with Jasper or VC Formal products is highly desirable
Experience in formal verification is a plus
Prior customer support experience is a plus
Experience with DevOps flows is a plus
Comfortable with co-developing an existing system