- Zettascale
- San Francisco, CA
- Full-Time
- 60 days ago
Founding Lead Silicon Engineer.
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Founding Lead Silicon Engineer: our view in 3 lines...
- The Role:This role leads silicon engineering for AI chips, taking the work from FPGA prototype through tapeout and bring-up.
- The Person:The person will lead FPGA prototype development, design and review RTL, build verification and timing flows, make architecture decisions, and drive the design through tapeout and bring-up.
- Requirements:The ideal candidate has strong digital design fundamentals, hands-on FPGA experience, synthesizable SystemVerilog or Verilog, and fluency with simulation, linting, synthesis, SDC constraints, timing closure, and CDC.
About the role
The Mission
Zettascale Computing is building the highest-performance, most energy-efficient AI chips for artificial superintelligence to accelerate discovery and further humanity's understanding of the universe.
We are a high-agency, deeply technical, and intensely mission-driven founding team. We value first principles thinking, intellectual honesty, speed, and full ownership.
The Role
Lead Zettascale Computing's silicon efforts from FPGA prototype through tapeout and bring-up. You will set technical direction across architecture, RTL, verification, tooling, and timing closure, build the silicon team as the company grows, and partner closely with the PCB, interconnects, racks and pods, and software teams.
What You Will Build
- Lead development and optimization of the FPGA prototype of our XPU
- Design and review the RTL that becomes our first ASIC
- Build the lint, simulation, synthesis, timing, and verification flows
- Make architecture decisions across compute, memory, on-chip interconnect, and control
- Drive the design to tapeout and bring-up
What You Bring
- Strong digital design fundamentals, including RTL, pipelining, clocks, resets, latency, throughput, and clean microarchitecture
- Hands-on FPGA experience taking real designs from RTL to a working board
- Synthesizable SystemVerilog or Verilog you are proud of
- Fluency with simulation, linting, synthesis, SDC constraints, timing closure, and CDC
- Experience automating hardware flows with Python, Tcl, Make, Nix, or similar tools
- Comfort designing compute datapaths and memory systems around bandwidth and latency
- Experience with AI accelerators or low-level AI kernels
- A proven autodidact
Tapeout experience, large FPGA prototypes, high-speed interface integration, formal verification, UVM, cocotb, firmware, drivers, and systems programming are strong advantages.
Expectations
- This is a full-time, in-person role at our San Francisco HQ. It is not remote or hybrid
- You move quickly, take broad ownership, and prefer working hardware over perfect specifications
- We do not track hours. We care about output, quality, and throughput
- Critical tapeout, bring-up, and delivery milestones sometimes require long days and weekends. We expect you to lean in when they do
- You are ready to go all-in and do the work of your life
Compensation and Support
- $200,000 to $300,000 base salary
- 1.00% to 3.00% equity
- Medical, dental, and vision coverage
- 401(k), equipment, and gym support
- Relocation assistance to San Francisco
- Visa sponsorship where feasible
- First interview
- Technical screening
- In-person full-day technical screening at our office
- Work trial, 1-4 weeks
- Offer
Building energy-efficient chips ("XPUs") to accelerate AI discovery.
Our XPUs highly programmable, capable of optimizing the dataflow of each model, making them faster and more energy-efficient than the current SOTA GPUs on the market. This saves data centers billions in cooling and energy costs.

